1. Field of the Invention
The present invention relates to a vector processing device that processes a large quantity of data by a single instruction.
2. Description of the Related Art
A vector processing device has a plurality of pipelines, and carries out a complex process by of the pipelines. Therefore a large quantity of data can be processed at a high speed. Normally, the vector processing device includes an instruction executing unit composed of a vector unit and a scaler unit, a main memory unit, and a memory control unit. The vector unit includes a vector register, and operation pipelines of addition, multiplication and division. Data to be operated on, that is, operation data is read from the main memory unit and is stored in a data buffer provided in the memory control unit. Thereafter, the operation data is read from the data buffer and is loaded to the vector register. The operation data is operated on by the operation pipelines in accordance with a vector instruction. The result of the operation is transferred from the vector unit, and is stored in the data buffer in the memory control unit. Thereafter, the operation result is stored in the main memory unit.
Recently, the vector processing device have employed a chaining process for vector registers in to process data at a high speed. The chaining of vector registers is such that, when a vector register, in which the operation result of a preceding vector instruction is stored, is referenced to by a subsequent vector instruction, execution of the subsequent vector instruction is started before the preceding instruction writes all data into the vector register.
The chaining of vector registers involves a major problem to be solved. That is, when the preceding vector instruction is a load instruction, vector data is not supplied to the operation pipelines executing the subsequent vector instruction each cycle due to a collision that occurs when accessing the main memory unit. In this case, the process cannot be correctly performed. To avoid the above situation, it is necessary to stop temporarily from operating the operation pipelines executing the subsequent vector instruction and a data transfer pipeline. Hence the reading of data from the vector registers is interrupted. The present invention was made with the above background in mind.